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1/26 NJW1230 ver.2.0e 1ch video amplifier & 2vrms ground referenced stereo line amplifier q general description q package outline the NJW1230 is an audio line amplifier with 1ch video amplifiier. audio line amplifier can swing 2vrms (5.6v peak-to-peak) signal at 3.3v operating voltage. ground-referenced outputs eliminat e output coupling capacitor. the pop noise suppression circuit removes a pop noise at the power-on and power-off. video amplifier contained lpf circuit. internal 75 ? driver is easy to connect tv monitor directly. q application o blu-ray/dvd player o home theater/set top box o av receiver q features o operating voltage 2.7 to 3.6v o power save circuit o package outline ssop16 audio block o output coupling capacitor-less o pop noise suppression circuit video block o lpf 4.5mhz o 6db amplifier o 75 ? driver (2-system drive) q block diagram NJW1230v v+1 gnd1 charge pump bias line inl 1st order lpf outl inr outr 1st order lpf line vin vout clamp 6db 75 ? driver vs cp cn v- bias ps 4.5mhz lpf v+2 gnd2
2/26 NJW1230 q pin configuration ssop16 no. symbol function 1 v+1 v+ power supply for audio 2 cp flying capacitor positive terminal for audio 3 cn flying capacitor negative terminal for audio 4 v- v- power supply for audio 5 mute mute / pop noise suppression for audio 6 gnd1 ground for audio 7 vin video input 8 vs sag correction 9 vout video output 10 ps powe save for video 11 gnd2 ground for video 12 v+2 v+ power supply for video 13 outr rch output 14 inr rch input 15 inl lch input 16 outl lch output 116 9 8
3/26 NJW1230 q absolute maximum rating (ta=25 c) parameter symbol rating unit supply voltage v + 4 v power dissipation p d 430 (note1) mw maximum input voltage v in -0.3 to v + +0.3 v operating temperature range topr -40 to +85 c storage temperature range tstg -40 to + 125 c (note1) eia/jedec standard test board (76. 2x114.3x1.6mm, 2layer, fr-4) mounting q recommended operating conditions (ta=25 c unless otherwise specified ) parameter symbol test condit ion min. typ. max. unit v +1 1pin 2.7 3.3 3.6 v operating voltage v +2 12pin 2.7 3.3 3.6 q electrical characteristics ? audio characteristics (ta=25 c, v + =3.3v, f=1khz, vin=1vrms, mute=off, r l =47k ? unless otherwise specified ) parameter symbol test condit ion min. typ. max. unit operating current i dd no signal - 5 10 ma output gain g v 5.2 6.2 7.2 db output gain error ? g v -0.5 0 0.5 db maximum output voltage level v omax thd=1% - 2.2 - vrms mute level v mute rg=0 ? , mute=on - -110 - db equivalent input noise voltage v no rg=0 ? , bw:400hz-22khz - -106 - db total harmonic distortion thd bw:400hz-22khz - 0.003 - % channel separation cs rg=600 ? 80 - - db cut-off frequency f c 2 nd lpf 100 150 200 khz output offset voltage vos rg=0 ? - 1 5 mv power supply rejection ratio psrr vripple=1khz / 100mvrms - 45 - db mute high level muteh mute=off 0.8v + - v + v mute low level mutel mute=on 0 - 0. 2 v + v ? control characteristics parameter status note h off(active) mute l on (mute)
4/26 NJW1230 ? video characteristics (ta=25 c , v + =3.3v, r l =150 ? , unless otherwise specified) parameter symbol test condi tion min. typ. max. unit operating current i cc no signal - 8.0 12.0 ma operating current at power save isave no signal, power save mode - 30 50 a maximum output voltage swing vom f=100khz,thd=1% 2.2 2.5 - vp-p voltage gain gv vin=100khz, 1.0vp-p,input sine signal 5.6 6.0 6.4 db gfy4.5m vin=4.5mhz/100khz, 1.0vp-p -0.6 -0.1 0.4 low pass filter characteristic gfy19m vin=19mhz/100khz, 1.0vp-p - -33 -23 db differential gain dg vin=1.0vp- p, 10step video signal - 0.5 - % differential phase dp vin=1.0vp- p, 10step video signal - 0.5 - deg s/n ratio snv vin=1.0vp-p, r l =75 ? 100% white video signal, 100khz to 6mhz - 65 - db power save high level vthh active 1.8 - v + power save low level vthl non-active 0 - 0.3 v ? control characteristics parameter status note h power save: off(active) power save l power save: on (mute)
5/26 NJW1230 q application circuit 1(video output is ac coupling ) gnd z bias1 v+1 10uf mute cp cn v- regulator 10u inl outl 1uf + 22k ? 4.7uf 400k ? 0.1uf clamp lpf +6db outr bias2 v+2 gnd1 gnd2 ps vout vs vin inr 0.1uf 10uf + 0.1uf 820pf 1k ? 1uf 820pf 1k ? 75 ? 100uf + 1uf + 22uf
6/26 NJW1230 q application circuit 2(video output is ac coupling 2-drive) note) when ac coupling and the video output connect two line of 150 ? ,connect the coupling capacitor after connecting the vout pin and vsag pin. the recommended value is 470f or more. gnd z bias1 v+1 10uf mute cp cn v- regulator 10uf inl outl 1uf + 22k ? 4.7uf 400k ? 0.1uf clamp lpf +6db outr bias2 v+2 gnd1 gnd2 ps vout vs vin inr 0.1uf 10uf + 0.1uf 820pf 1k ? 1uf 820pf 1k ? + 75 ? 470u + inr 1uf 75 ?
7/26 NJW1230 q application circuit 2(video output is dc coupling ) note) vout outputs dc of 0.33v. gnd z bias1 v+1 10uf mute cp c n v- regulator 10uf inl outl 1uf + 22k ? 4.7uf 400k ? 0.1uf clamp lpf +6db outr bias2 v+2 gnd1 gnd2 ps vout vs vin inr 0.1uf 10uf + 0.1uf 820pf 1k ? 1uf 820pf 1k ? + 75 ? inr 1uf 75 ?
8/26 NJW1230 ? application note NJW1230 built in stereo line amplifier. stereo line amplifie r is that eliminates the need for external dc-blocking output capacitors. also built in pop suppression circuitr y to eliminate disturbing pop noise during power-on, power-off and mute-control. video block is low voltage operate video amplifier with lpf. it direct coupling to tv monitor with built in 75 ? - driver. it is able to both ac ? coupling and dc ? coupling. input signal is cvbs, also suitability low power application with built in power save circuit 1. audio block?s operating principle audio block of NJW1230 is stereo line amplifier. it has the built-in non-inverted input operational amplifiers, voltage inverter, and pop noise suppression circuitry (fig.1). the voltage inverter for stereo line amplifier eliminates the need for external dc-blocking output capacitors. the pop suppression circuitry for stereo line amplifie r eliminates the pop noise during power-on, power-off and mute-control. fig.1 NJW1230 block diagram gnd z bias1 v+1 10uf mute cp c n v- regulator 10uf inl outl 1uf + 22k ? 4.7uf 400k ? 0.1uf clamp lpf +6db outr bias2 v+2 gnd1 gnd2 ps vout vs vin inr 0.1uf 10uf + 0.1uf 820pf 1k ? 1uf 820pf 1k ? + 75 ? inr 1uf (chip) mute-tr mute-tr pop noise suppression c2 c3 c4 c6 c11 c12 c8 c9 c7 r1 r2 r3 + + 33uf 33uf audio block video block
9/26 NJW1230 1.1 external parts 1.1.1 input coupling capacitors c i (c2, c8) the input coupling capacitor (c i ) and the total of the external re sistance (r1, r3) and the input resistance (r in =218k ? typ.) for the non-inverted terminal form a hi gh-pass filter with the corner frequency determined in [fc=1/(2 x (r1+218k ?) x c i )). it is necessary to adjust 1uf or more. 1.1.2 flying capacitor (c4) use capacitors with a low-esr (ex. ceramic capaci tors) for optimum performance. design to provide low impedance for the wiring between cp terminal ( 2pin), cn terminal (3pin), and the flying capacitor (c4). fig.2 external circuit of 2pin, 3pin 1.1.3 hold capacitor (c6) use capacitors with a low-esr (ex. ceramic capaci tors) for optimum performance. design to provide low impedance for the wiring between the hold capacitor (c6), v- terminal (6pin) and the gnd on the pcb. separate the gnd pattern connecting to the hold capacitor (c6) from that connecting to the gnd terminal (6pin), thus suppressing the influence of sw itching noise by removing the common impedance of the gnd wiring. design no short-circuits of v- terminal (4pin) and v+ terminal (1pin) on the pcb pattern. fig.3 external circuit of 4pin, 6pin 1.1.4 mute terminal pop noise countermeasures (r2, c7) mute terminal (5pin) needs time constant more than r2 x c7=0.1. it is necessary to adjust 22k ? or less. fig.4 external circuit of 5pin cp (2pin) cn (3pin) c4=1uf v- (4pin) gnd 1 (6pi n) c6 mute (5pin) c7=4.7uf r2=22k ? vcnt 400k ?
10/26 NJW1230 1.2 control of v+ terminal and mute terminal 1.2.2 power-on procedure 1. turn on the v+. 2. after 100msec from power on, change the control voltage of mute terminal (vcnt) from "low" to "high". * it is necessary to stabilize an ic for 100msec. by releasing the mute function, the output terminal output the signal. 1.2.3 power-off procedure 1. change the control voltage of mute term inal (vcnt) from "high" to "low". by the mute function, the output sig nals are stopped from output terminal. 2. turn off the v+ after ?2rc? sec from mute. * it is necessary to stabilize a mute condition for ?2rc? sec. ex.) r2=22k ? , c7=4.7uf -> 2r2 x c7=200msec fig.5 power-on / power-off timing chart v+1 (1pin) vc n t mu te (5pin) 100mse 200mse mute on mute off mute on t t t
11/26 NJW1230 2. video block?s operating principle video block is low voltage video amplifier with lpf. it direct coupling to tv monitor with built in 75 ? - driver. it is able to both ac ? co upling and dc ? coupling. input signal is cvbs, also suitability low power application with built in power save circuit 2.1 typical application circuit (at use sag collection circuit) this application circuit is deal with the possibility of portable system that be bound by space. it can make output capacitor smaller by sag collection circuit. however, this circuit has possibilities deterioration of sag, and get out synchronization at rapid changes in brightness of input signal. therefore we recommend measurement at comprehend low frequency of input signal (ex. white ? black bounce signal). fig.6 typical application circuit 2.2 unused sag collection circuit we recommend unused sag collection circuit at be not bound by space. connect with vout terminal and vsag terminal. then connect to out put capacitor of over 470uf. fig.7 unused sag collection circuit 2.3 two drive application circuit this circuit can drive 150 ? x2. however get out synchronization at rapid changes in brightness of input signal. we recommend measurement at comprehend low frequency of input signal (ex. white ? black bounce signal). fig.7 two drive application circuit vsag (8pin) vo ut (9pin) 75 ? + + 33uf 33uf c1 vsag (8pin) vo ut (9pi n) 75 ? + 470uf vs ag (8pin) vo ut (9pi n) 75 ? + 470uf 75 ?
12/26 NJW1230 2.4 dc ? coupling application circuit vout terminal output 0.33v all of the time. fig.8 dc ? coupling application circuit 3. how to trace v+1(1pin), v+2( 12pin), gnd1(6pin), gnd2(11pin) v+1 and gnd1 for audio block. v+2 and gnd2 for video bl ock. audio block built in charge pump circuit. as a result, clock noise of charge pump circ uit on between v+1 and gnd1. video output is take a leaf from clock noise at clock noise on between v+2 and gnd2. each terminal make a separation trace. cut down common impedance of between audio block and video block. fig.9 external circuit of 1pin, 6pin, 11pin, 12pin vs ag (8pin) vo ut (9pi n) 75 ? 75 ? gnd1 (6pin) gnd2 (11pin) v+1 (1pin) v+2 (12pin)
13/26 NJW1230 ? sag correction circuit sag correction circuit is a circuit to correct for low-frequency attenuation by high-pass filter consisting of the output coupling capacitance and load resistance. low-frequency attenuation raises the sag in the vertical period of the video signal. capacitor for vsag (csag) is connected to the negative feedback of the amplifier. this csag increase the low frequency gain to correct for the attenuation of low frequency gain. example sag collection circuit example of not using sag compensation circuit waveform of vout terminal and vout1 terminal using sag correction circuit not using sag correction circuit waveform of vout waveform of vout waveform of vout1 waveform of vout1 1vertical period vout vsag cout vout1 resistance:rl vout vsag cout csag vout1 resistance:rl 1vertical period
14/26 NJW1230 sag correction circuit generates a low frequency component signal amplified to vout terminal. changes of the luminance signal will be low-frequency co mponents, if you want to out put a large sig nal luminance changes. therefore, generate correction signal of change of a luminance signal to vout pin. at this time, signal is over the dynamic range of vout pin. this may cause a lack of sync signal, and waveform distortion. please see diagram below (green waveform ), if you want to output large changes of a signal luminance, such as 100% white video signal and black signal. thus, output si gnal exceed dynamic range of vout pin and may be the signal lack. < countermeasure for waveform distortion > 1. please using small value the s ag compensation capacitor (vsag). it can ensure the dynamic range by us ing small value the capacitor (vsag ). it because of low-frequency variation of vout pin is smaller. however, the output (vout) must be use large capacitor for this reason sag characteristics become exacerbated. 2. please do not use the sag correction circuit. signal can output within dynamic range for reason it does not change the dc level of the output terminal. however, the output (vout) must be use large capaci tor for this reason sag characteristics become exacerbated. input signal the sync signal is missing because exceed the dynamic range of vout. waveform of vout1 waveform of vout dynamic range of vout
15/26 NJW1230 < dual drive at using sag correction circuit > using sag correction circuit at dual drive circuit is below. dual drives are less load resistance. thus, the cut-off frequency of hpf that is composed of the output capacitor and load resistan ce will be small. therefore, the sag characteristics deteriorate. please size up to the output capacitor (vout) fo r not to deteriorate the sag characteristics. < dual drive at not using sag correction circuit > we recommended two-example dual drive circuit with not use sag correction circuit. please change the configuration to be used according to the situation. pleas e configure to meet the following conditions. then you can adjust the characteristi cs of each configuration. 2 1 cout cout cout + = 2 1 cout cout = (a) in case of using one output capacitor (b) in case of using two output capacitors
16/26 NJW1230 < using sag correction circuit > input signal: bounce signal (ire 0%, ire100%, 30hz), resistance=150 ? waveform: yellow: input signal, green: vout signal, purple: vout1signal csag=10uf csag=22uf csag=33uf cout=33uf cout=47uf cout=100uf cout=220uf cout=330uf
17/26 NJW1230 input signal: bounce signal (ire 0%, ire100%, 30hz), resistance=75 ? waveform: yellow: input signal, green: vout signal, purple: vout1signal csag=10uf csag=22uf csag=33uf cout=100uf cout=220uf cout=330uf cout=470uf cout=1000uf
18/26 NJW1230 < not using sag correction circuit > input signal: bounce signal (ire 0%, ire100%, 30hz), resistance=150 ? waveform: yellow: input signal, green: vout signal, purple: vout1signal rl=75 ? rl=150 ? cout=100uf cout=220uf cout=330uf cout=470uf cout=1000uf
19/26 NJW1230 < using sag correction circuit > input signal: black to white100%, resistance150 ? waveform: yellow: input signal, green: vout signal, purple: vout1signal csag=10uf csag=22uf csag=33uf cout=33uf cout=47uf cout=100uf cout=220uf cout=330uf
20/26 NJW1230 input signal: white100% to black, resistance150 ? waveform: yellow: input signal, green: vout signal, purple: vout1signal csag=10uf csag=22uf csag=33uf cout=33uf cout=47uf cout=100uf cout=220uf cout=330uf
21/26 NJW1230 < using sag correction circuit > input signal: black to white100%, resistance=75 ? waveform: yellow: input signal, green: vout signal, purple: vout1signal csag=10uf csag=22uf csag=33uf cout=33uf cout=47uf cout=100uf cout=220uf cout=330uf
22/26 NJW1230 input signal: white100% to black, resistance=75 ? waveform: yellow: input signal, green: vout signal, purple: vout1signal csag=10uf csag=22uf csag=33uf cout=33uf cout=47uf cout=100uf cout=220uf cout=330uf
23/26 NJW1230 ? clamp circuit 1. operation of sync-tip-clamp input circuit will be explained. sync-tip clamp circuit (below the clamp circ uit) operates to keep a sync tip of the minimum potential of the video signal. clamp circuit is a circuit of the capacitor charging and discharging of the external input cin. it is charged to the capacitor to the external input cin at sync tip of the video signal. therefore, the potential of the sync tip is fixed. and it is discharged charge by capacito r cin at period other than the video signal sync tip. this is due to a small discharge current to the ic. in this way, this clamp circuit is fixed sync tip of video signal to a constant potential from charging of cin and discharging of cin at every one horizontal period of the video signal. the minute current be discharged an electrical charge fr om the input capacitor at the period other than the sync tip of video signals. decrease of voltage on dischar ge is dependent on the size of the input capacitor cin. if you decrease the value of the input capacitor, will ca use distortion, called the h sag. therefore, the input capacitor recommend on more than 0.1uf. < clamp circuit > a. cin is large b. cin is small (h sag experience) < waveform of input terminal > 2. input impedance the input impedance of the clamp circuit is different at the capacitor discharge period and the charge period. the input impedance of the charging period is a few k ? . on the other hand, the input impedance of the discharge period is several m ? . because is a small discharge-current through to the ic. thus the input impedance will vary depending on the operating state of the clamp circuit. 3. impedance of signal source source impedance to the input terminal, please lower than 200 ? . a high source impedance, the signal may be distorted. if so, please to connect a buffer for impedance conversion. cin vin clamp circuit charge curren t diccharge curren t signal input charge period discharge period clamp potential charge period clamp potential charge period discharge period charge period
24/26 NJW1230 ? terminal description terminal symbol function equivalent circuit voltage 1 v+1 v+ power supply for audio 2 cn flying capacitor negative terminal for audio - 3 cp flying capacitor positive terminal for audio - 4 v- v- power supply for audio -[v+] 5 mute mute / pop noise suppression for audio 0v v- v+ v+ v- gnd v- v+ 100 ? v- v+ 400k ? gnd v- v+ gnd
25/26 NJW1230 ? terminal description terminal symbol function equivalent circuit voltage 7 vin video input 1.10v 8 vs sag correction - 9 vout video output 0.33v 10 ps power save for video - 11 v+2 v+ power supply for video 3v v + 750 ? v + vsag v + v + vout v- v+ vin v + v + v + 270 ? 48k ? 32k ? 16k ? 16k ? gnd
26/26 NJW1230 ? terminal description terminal symbol function equivalent circuit voltage 15 14 inl inr audio input 0v 16 13 outl outr audio output 0v [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. 18k ? 30pf 200k ? v+ v- gnd 1k ? 300 ? v- gnd vdd 8.68k ? 14.8k ? 1k ?

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